Types

VerilogNodeKind = enum verilogDollarfulskewUnderscoretimingUnderscorecheck, ## $fullskew_timing_check verilogDollarholdUnderscoretimingUnderscorecheck, ## $hold_timing_check verilogDollarnochangeUnderscoretimingUnderscorecheck, ## $nochange_timing_check verilogDollarperiodUnderscoretimingUnderscorecheck, ## $period_timing_check verilogDollarrecoveryUnderscoretimingUnderscorecheck, ## $recovery_timing_check verilogDollarrecremUnderscoretimingUnderscorecheck, ## $recrem_timing_check verilogDollarremovalUnderscoretimingUnderscorecheck, ## $removal_timing_check verilogDollarsetupUnderscoretimingUnderscorecheck, ## $setup_timing_check verilogDollarsetupholdUnderscoretimingUnderscorecheck, ## $setuphold_timing_check verilogDollarskewUnderscoretimingUnderscorecheck, ## $skew_timing_check verilogDollartimeskewUnderscoretimingUnderscorecheck, ## $timeskew_timing_check verilogDollarwidthUnderscoretimingUnderscorecheck, ## $width_timing_check verilogOrderedParameterAssignment, ## _ordered_parameter_assignment verilogActionBlock, ## action_block verilogAlwaysConstruct, ## always_construct verilogAlwaysKeyword, ## always_keyword verilogAnonymousProgram, ## anonymous_program verilogAnonymousProgramItem, ## anonymous_program_item verilogAnsiPortDeclaration, ## ansi_port_declaration verilogArrayManipulationCall, ## array_manipulation_call verilogArrayMethodName, ## array_method_name verilogArrayRangeExpression, ## array_range_expression verilogAssertPropertyStatement, ## assert_property_statement verilogAssertionVariableDeclaration, ## assertion_variable_declaration verilogAssignmentOperator, ## assignment_operator verilogAssignmentPattern, ## assignment_pattern verilogAssignmentPatternExpression, ## assignment_pattern_expression verilogAssignmentPatternKey, ## assignment_pattern_key verilogAssignmentPatternNetLvalue, ## assignment_pattern_net_lvalue verilogAssignmentPatternVariableLvalue, ## assignment_pattern_variable_lvalue verilogAssociativeDimension, ## associative_dimension verilogAssumePropertyStatement, ## assume_property_statement verilogAttrSpec, ## attr_spec verilogAttributeInstance, ## attribute_instance verilogBeginKeywords, ## begin_keywords verilogBindDirective, ## bind_directive verilogBindTargetInstance, ## bind_target_instance verilogBindTargetInstanceList, ## bind_target_instance_list verilogBindTargetScope, ## bind_target_scope verilogBinsExpression, ## bins_expression verilogBinsKeyword, ## bins_keyword verilogBinsOrEmpty, ## bins_or_empty verilogBinsOrOptions, ## bins_or_options verilogBinsSelection, ## bins_selection verilogBinsSelectionOrOption, ## bins_selection_or_option verilogBitSelect1, ## bit_select1 verilogBlockEventExpression, ## block_event_expression verilogBlockItemDeclaration, ## block_item_declaration verilogBlockingAssignment, ## blocking_assignment verilogCaseExpression, ## case_expression verilogCaseGenerateConstruct, ## case_generate_construct verilogCaseGenerateItem, ## case_generate_item verilogCaseInsideItem, ## case_inside_item verilogCaseItem, ## case_item verilogCaseItemExpression, ## case_item_expression verilogCaseKeyword, ## case_keyword verilogCasePatternItem, ## case_pattern_item verilogCaseStatement, ## case_statement verilogCast, ## cast verilogCastingType, ## casting_type verilogCellClause, ## cell_clause verilogCellIdentifier, ## cell_identifier verilogChargeStrength, ## charge_strength verilogCheckerDeclaration, ## checker_declaration verilogCheckerIdentifier, ## checker_identifier verilogCheckerInstantiation, ## checker_instantiation verilogCheckerOrGenerateItemDeclaration, ## checker_or_generate_item_declaration verilogCheckerPortDirection, ## checker_port_direction verilogCheckerPortItem, ## checker_port_item verilogCheckerPortList, ## checker_port_list verilogClassConstructorDeclaration, ## class_constructor_declaration verilogClassConstructorPrototype, ## class_constructor_prototype verilogClassDeclaration, ## class_declaration verilogClassIdentifier, ## class_identifier verilogClassItem, ## class_item verilogClassItemQualifier, ## class_item_qualifier verilogClassMethod, ## class_method verilogClassNew, ## class_new verilogClassProperty, ## class_property verilogClassQualifier, ## class_qualifier verilogClassScope, ## class_scope verilogClassType, ## class_type verilogClockingDeclAssign, ## clocking_decl_assign verilogClockingDeclaration, ## clocking_declaration verilogClockingDirection, ## clocking_direction verilogClockingDrive, ## clocking_drive verilogClockingEvent, ## clocking_event verilogClockingIdentifier, ## clocking_identifier verilogClockingItem, ## clocking_item verilogClockingSkew, ## clocking_skew verilogClockvar, ## clockvar verilogClockvarExpression, ## clockvar_expression verilogCmosSwitchInstance, ## cmos_switch_instance verilogCmosSwitchtype, ## cmos_switchtype verilogCombinationalBody, ## combinational_body verilogCombinationalEntry, ## combinational_entry verilogConcatenation, ## concatenation verilogConcurrentAssertionItem, ## concurrent_assertion_item verilogCondPattern, ## cond_pattern verilogCondPredicate, ## cond_predicate verilogConditionalExpression, ## conditional_expression verilogConditionalStatement, ## conditional_statement verilogConfigIdentifier, ## config_identifier verilogConfigRuleStatement, ## config_rule_statement verilogConsecutiveRepetition, ## consecutive_repetition verilogConstIdentifier, ## const_identifier verilogConstantBitSelect1, ## constant_bit_select1 verilogConstantConcatenation, ## constant_concatenation verilogConstantExpression, ## constant_expression verilogConstantIndexedRange, ## constant_indexed_range verilogConstantMintypmaxExpression, ## constant_mintypmax_expression verilogConstantMultipleConcatenation, ## constant_multiple_concatenation verilogConstantParamExpression, ## constant_param_expression verilogConstantPrimary, ## constant_primary verilogConstantRange, ## constant_range verilogConstantSelect1, ## constant_select1 verilogConstraintBlock, ## constraint_block verilogConstraintBlockItem, ## constraint_block_item verilogConstraintDeclaration, ## constraint_declaration verilogConstraintExpression, ## constraint_expression verilogConstraintIdentifier, ## constraint_identifier verilogConstraintPrimary, ## constraint_primary verilogConstraintPrototype, ## constraint_prototype verilogConstraintPrototypeQualifier, ## constraint_prototype_qualifier verilogConstraintSet, ## constraint_set verilogContinuousAssign, ## continuous_assign verilogControlledReferenceEvent, ## controlled_reference_event verilogCoverCross, ## cover_cross verilogCoverPoint, ## cover_point verilogCoverPointIdentifier, ## cover_point_identifier verilogCoverPropertyStatement, ## cover_property_statement verilogCoverSequenceStatement, ## cover_sequence_statement verilogCoverageEvent, ## coverage_event verilogCoverageOption, ## coverage_option verilogCoverageSpecOrOption, ## coverage_spec_or_option verilogCovergroupDeclaration, ## covergroup_declaration verilogCovergroupIdentifier, ## covergroup_identifier verilogCovergroupRangeList, ## covergroup_range_list verilogCovergroupValueRange, ## covergroup_value_range verilogCrossBody, ## cross_body verilogCrossBodyItem, ## cross_body_item verilogCrossIdentifier, ## cross_identifier verilogCycleDelay, ## cycle_delay verilogCycleDelayConstRangeExpression, ## cycle_delay_const_range_expression verilogCycleDelayRange, ## cycle_delay_range verilogDataDeclaration, ## data_declaration verilogDataEvent, ## data_event verilogDataSourceExpression, ## data_source_expression verilogDataType, ## data_type verilogDataTypeOrImplicit1, ## data_type_or_implicit1 verilogDataTypeOrVoid, ## data_type_or_void verilogDecimalNumber, ## decimal_number verilogDefaultClause, ## default_clause verilogDefaultNettypeCompilerDirective, ## default_nettype_compiler_directive verilogDefaultNettypeValue, ## default_nettype_value verilogDefaultSkew, ## default_skew verilogDeferredImmediateAssertStatement, ## deferred_immediate_assert_statement verilogDeferredImmediateAssertionItem, ## deferred_immediate_assertion_item verilogDeferredImmediateAssumeStatement, ## deferred_immediate_assume_statement verilogDeferredImmediateCoverStatement, ## deferred_immediate_cover_statement verilogDefparamAssignment, ## defparam_assignment verilogDelay2, ## delay2 verilogDelay3, ## delay3 verilogDelayControl, ## delay_control verilogDelayOrEventControl, ## delay_or_event_control verilogDelayValue, ## delay_value verilogDelayedData, ## delayed_data verilogDelayedReference, ## delayed_reference verilogDesignStatement, ## design_statement verilogDisableStatement, ## disable_statement verilogDistItem, ## dist_item verilogDistList, ## dist_list verilogDistWeight, ## dist_weight verilogDoubleQuotedString, ## double_quoted_string verilogDpiFunctionImportProperty, ## dpi_function_import_property verilogDpiFunctionProto, ## dpi_function_proto verilogDpiImportExport, ## dpi_import_export verilogDpiSpecString, ## dpi_spec_string verilogDpiTaskImportProperty, ## dpi_task_import_property verilogDpiTaskProto, ## dpi_task_proto verilogDriveStrength, ## drive_strength verilogDynamicArrayNew, ## dynamic_array_new verilogEdgeControlSpecifier, ## edge_control_specifier verilogEdgeDescriptor, ## edge_descriptor verilogEdgeIdentifier, ## edge_identifier verilogEdgeIndicator, ## edge_indicator verilogEdgeInputList, ## edge_input_list verilogEdgeSensitivePathDeclaration, ## edge_sensitive_path_declaration verilogElaborationSystemTask, ## elaboration_system_task verilogEmptyUnpackedArrayConcatenation, ## empty_unpacked_array_concatenation verilogEnableGateInstance, ## enable_gate_instance verilogEnableGatetype, ## enable_gatetype verilogEnableTerminal, ## enable_terminal verilogEndEdgeOffset, ## end_edge_offset verilogEnumBaseType, ## enum_base_type verilogEnumIdentifier, ## enum_identifier verilogEnumNameDeclaration, ## enum_name_declaration verilogErrorLimitValue, ## error_limit_value verilogEscapedIdentifier, ## escaped_identifier verilogEventBasedFlag, ## event_based_flag verilogEventControl, ## event_control verilogEventExpression, ## event_expression verilogEventTrigger, ## event_trigger verilogExpectPropertyStatement, ## expect_property_statement verilogExpression, ## expression verilogExpressionOrDist, ## expression_or_dist verilogExternConstraintDeclaration, ## extern_constraint_declaration verilogExternTfDeclaration, ## extern_tf_declaration verilogFinalConstruct, ## final_construct verilogFinishNumber, ## finish_number verilogForInitialization, ## for_initialization verilogForStep, ## for_step verilogForVariableDeclaration, ## for_variable_declaration verilogFormalArgument, ## formal_argument verilogFormalIdentifier, ## formal_identifier verilogFormalPortIdentifier, ## formal_port_identifier verilogFullEdgeSensitivePathDescription, ## full_edge_sensitive_path_description verilogFullPathDescription, ## full_path_description verilogFunctionBodyDeclaration, ## function_body_declaration verilogFunctionDataTypeOrImplicit1, ## function_data_type_or_implicit1 verilogFunctionDeclaration, ## function_declaration verilogFunctionIdentifier, ## function_identifier verilogFunctionPrototype, ## function_prototype verilogFunctionStatement, ## function_statement verilogFunctionStatementOrNull, ## function_statement_or_null verilogFunctionSubroutineCall, ## function_subroutine_call verilogGateInstantiation, ## gate_instantiation verilogGenerateBlock, ## generate_block verilogGenerateBlockIdentifier, ## generate_block_identifier verilogGenerateRegion, ## generate_region verilogGenvarDeclaration, ## genvar_declaration verilogGenvarIdentifier, ## genvar_identifier verilogGenvarInitialization, ## genvar_initialization verilogGenvarIteration, ## genvar_iteration verilogGotoRepetition, ## goto_repetition verilogHierarchicalBtfIdentifier, ## hierarchical_btf_identifier verilogHierarchicalInstance, ## hierarchical_instance verilogIdDirective, ## id_directive verilogIdentifierList, ## identifier_list verilogIfGenerateConstruct, ## if_generate_construct verilogImplicitClassHandle, ## implicit_class_handle verilogImplicitDataType1, ## implicit_data_type1 verilogImportExport, ## import_export verilogIncOrDecExpression, ## inc_or_dec_expression verilogIncOrDecOperator, ## inc_or_dec_operator verilogIncludeCompilerDirective, ## include_compiler_directive verilogIncludeCompilerDirectiveStandard, ## include_compiler_directive_standard verilogIndexVariableIdentifier, ## index_variable_identifier verilogIndexedRange, ## indexed_range verilogInitVal, ## init_val verilogInitialConstruct, ## initial_construct verilogInoutDeclaration, ## inout_declaration verilogInoutPortIdentifier, ## inout_port_identifier verilogInoutTerminal, ## inout_terminal verilogInputDeclaration, ## input_declaration verilogInputIdentifier, ## input_identifier verilogInputPortIdentifier, ## input_port_identifier verilogInputTerminal, ## input_terminal verilogInsideExpression, ## inside_expression verilogInstClause, ## inst_clause verilogInstName, ## inst_name verilogInstanceIdentifier, ## instance_identifier verilogIntegerAtomType, ## integer_atom_type verilogIntegerVectorType, ## integer_vector_type verilogIntegralNumber, ## integral_number verilogInterfaceAnsiHeader, ## interface_ansi_header verilogInterfaceClassDeclaration, ## interface_class_declaration verilogInterfaceClassItem, ## interface_class_item verilogInterfaceClassMethod, ## interface_class_method verilogInterfaceClassType, ## interface_class_type verilogInterfaceDeclaration, ## interface_declaration verilogInterfaceIdentifier, ## interface_identifier verilogInterfaceInstanceIdentifier, ## interface_instance_identifier verilogInterfaceInstantiation, ## interface_instantiation verilogInterfaceItem, ## interface_item verilogInterfaceNonansiHeader, ## interface_nonansi_header verilogInterfaceOrGenerateItem, ## interface_or_generate_item verilogInterfacePortDeclaration, ## interface_port_declaration verilogInterfacePortHeader, ## interface_port_header verilogJoinKeyword, ## join_keyword verilogJumpStatement, ## jump_statement verilogLetActualArg, ## let_actual_arg verilogLetDeclaration, ## let_declaration verilogLetExpression, ## let_expression verilogLetFormalType1, ## let_formal_type1 verilogLetListOfArguments, ## let_list_of_arguments verilogLetPortItem, ## let_port_item verilogLetPortList, ## let_port_list verilogLevelInputList, ## level_input_list verilogLiblistClause, ## liblist_clause verilogLibraryIdentifier, ## library_identifier verilogLifetime, ## lifetime verilogLimitValue, ## limit_value verilogLineCompilerDirective, ## line_compiler_directive verilogListOfActualArguments, ## list_of_actual_arguments verilogListOfArguments, ## list_of_arguments verilogListOfArgumentsParent, ## list_of_arguments_parent verilogListOfClockingDeclAssign, ## list_of_clocking_decl_assign verilogListOfCrossItems, ## list_of_cross_items verilogListOfDefparamAssignments, ## list_of_defparam_assignments verilogListOfFormalArguments, ## list_of_formal_arguments verilogListOfGenvarIdentifiers, ## list_of_genvar_identifiers verilogListOfInterfaceIdentifiers, ## list_of_interface_identifiers verilogListOfNetAssignments, ## list_of_net_assignments verilogListOfNetDeclAssignments, ## list_of_net_decl_assignments verilogListOfParamAssignments, ## list_of_param_assignments verilogListOfParameterAssignments, ## list_of_parameter_assignments verilogListOfPathDelayExpressions, ## list_of_path_delay_expressions verilogListOfPathInputs, ## list_of_path_inputs verilogListOfPathOutputs, ## list_of_path_outputs verilogListOfPortConnections, ## list_of_port_connections verilogListOfPortDeclarations, ## list_of_port_declarations verilogListOfPortIdentifiers, ## list_of_port_identifiers verilogListOfPorts, ## list_of_ports verilogListOfSpecparamAssignments, ## list_of_specparam_assignments verilogListOfTfVariableIdentifiers, ## list_of_tf_variable_identifiers verilogListOfTypeAssignments, ## list_of_type_assignments verilogListOfUdpPortIdentifiers, ## list_of_udp_port_identifiers verilogListOfVariableAssignments, ## list_of_variable_assignments verilogListOfVariableDeclAssignments, ## list_of_variable_decl_assignments verilogListOfVariableIdentifiers, ## list_of_variable_identifiers verilogListOfVariablePortIdentifiers, ## list_of_variable_port_identifiers verilogLocalParameterDeclaration, ## local_parameter_declaration verilogLoopGenerateConstruct, ## loop_generate_construct verilogLoopStatement, ## loop_statement verilogLoopVariables1, ## loop_variables1 verilogMemberIdentifier, ## member_identifier verilogMethodCall, ## method_call verilogMethodCallBody, ## method_call_body verilogMethodIdentifier, ## method_identifier verilogMethodQualifier, ## method_qualifier verilogMintypmaxExpression, ## mintypmax_expression verilogModportClockingDeclaration, ## modport_clocking_declaration verilogModportDeclaration, ## modport_declaration verilogModportIdentifier, ## modport_identifier verilogModportItem, ## modport_item verilogModportPortsDeclaration, ## modport_ports_declaration verilogModportSimplePort, ## modport_simple_port verilogModportSimplePortsDeclaration, ## modport_simple_ports_declaration verilogModportTfPortsDeclaration, ## modport_tf_ports_declaration verilogModuleAnsiHeader, ## module_ansi_header verilogModuleDeclaration, ## module_declaration verilogModuleHeader, ## module_header verilogModuleInstantiation, ## module_instantiation verilogModuleKeyword, ## module_keyword verilogModuleNonansiHeader, ## module_nonansi_header verilogModuleOrGenerateItem, ## module_or_generate_item verilogModulePathConcatenation, ## module_path_concatenation verilogModulePathExpression, ## module_path_expression verilogModulePathMintypmaxExpression, ## module_path_mintypmax_expression verilogModulePathMultipleConcatenation, ## module_path_multiple_concatenation verilogModulePathPrimary, ## module_path_primary verilogMosSwitchInstance, ## mos_switch_instance verilogMosSwitchtype, ## mos_switchtype verilogMultipleConcatenation, ## multiple_concatenation verilogNInputGateInstance, ## n_input_gate_instance verilogNInputGatetype, ## n_input_gatetype verilogNOutputGateInstance, ## n_output_gate_instance verilogNOutputGatetype, ## n_output_gatetype verilogNameOfInstance, ## name_of_instance verilogNamedParameterAssignment, ## named_parameter_assignment verilogNamedPortConnection, ## named_port_connection verilogNcontrolTerminal, ## ncontrol_terminal verilogNetAlias, ## net_alias verilogNetAssignment, ## net_assignment verilogNetDeclAssignment, ## net_decl_assignment verilogNetDeclaration, ## net_declaration verilogNetLvalue, ## net_lvalue verilogNetPortHeader1, ## net_port_header1 verilogNetPortType1, ## net_port_type1 verilogNetType, ## net_type verilogNetTypeDeclaration, ## net_type_declaration verilogNextState, ## next_state verilogNonConsecutiveRepetition, ## non_consecutive_repetition verilogNonIntegerType, ## non_integer_type verilogNonPortProgramItem, ## non_port_program_item verilogNonblockingAssignment, ## nonblocking_assignment verilogNonrangeSelect1, ## nonrange_select1 verilogNonrangeVariableLvalue, ## nonrange_variable_lvalue verilogNotifier, ## notifier verilogOpenRangeList, ## open_range_list verilogOpenValueRange, ## open_value_range verilogOperatorAssignment, ## operator_assignment verilogOrderedPortConnection, ## ordered_port_connection verilogOutputDeclaration, ## output_declaration verilogOutputIdentifier, ## output_identifier verilogOutputPortIdentifier, ## output_port_identifier verilogOutputTerminal, ## output_terminal verilogOverloadDeclaration, ## overload_declaration verilogOverloadOperator, ## overload_operator verilogOverloadProtoFormals, ## overload_proto_formals verilogPackageDeclaration, ## package_declaration verilogPackageExportDeclaration, ## package_export_declaration verilogPackageIdentifier, ## package_identifier verilogPackageImportDeclaration, ## package_import_declaration verilogPackageImportItem, ## package_import_item verilogPackageOrGenerateItemDeclaration, ## package_or_generate_item_declaration verilogPackageScope, ## package_scope verilogPackedDimension, ## packed_dimension verilogParBlock, ## par_block verilogParallelEdgeSensitivePathDescription, ## parallel_edge_sensitive_path_description verilogParallelPathDescription, ## parallel_path_description verilogParamAssignment, ## param_assignment verilogParamExpression, ## param_expression verilogParameterDeclaration, ## parameter_declaration verilogParameterIdentifier, ## parameter_identifier verilogParameterOverride, ## parameter_override verilogParameterPortDeclaration, ## parameter_port_declaration verilogParameterPortList, ## parameter_port_list verilogParameterValueAssignment, ## parameter_value_assignment verilogPassEnSwitchtype, ## pass_en_switchtype verilogPassEnableSwitchInstance, ## pass_enable_switch_instance verilogPassSwitchInstance, ## pass_switch_instance verilogPassSwitchtype, ## pass_switchtype verilogPathDeclaration, ## path_declaration verilogPathDelayExpression, ## path_delay_expression verilogPathDelayValue, ## path_delay_value verilogPattern, ## pattern verilogPcontrolTerminal, ## pcontrol_terminal verilogPolarityOperator, ## polarity_operator verilogPort, ## port verilogPortDeclaration, ## port_declaration verilogPortDirection, ## port_direction verilogPortIdentifier, ## port_identifier verilogPortReference, ## port_reference verilogPrimary, ## primary verilogPrimaryLiteral, ## primary_literal verilogProceduralContinuousAssignment, ## procedural_continuous_assignment verilogProceduralTimingControlStatement, ## procedural_timing_control_statement verilogProductionIdentifier, ## production_identifier verilogProgramAnsiHeader, ## program_ansi_header verilogProgramDeclaration, ## program_declaration verilogProgramIdentifier, ## program_identifier verilogProgramInstantiation, ## program_instantiation verilogProgramItem, ## program_item verilogProgramNonansiHeader, ## program_nonansi_header verilogPropertyCaseItem, ## property_case_item verilogPropertyDeclaration, ## property_declaration verilogPropertyExpr, ## property_expr verilogPropertyFormalType1, ## property_formal_type1 verilogPropertyIdentifier, ## property_identifier verilogPropertyListOfArguments, ## property_list_of_arguments verilogPropertyLvarPortDirection, ## property_lvar_port_direction verilogPropertyPortItem, ## property_port_item verilogPropertyPortList, ## property_port_list verilogPropertySpec, ## property_spec verilogPsIdentifier, ## ps_identifier verilogPsOrHierarchicalArrayIdentifier, ## ps_or_hierarchical_array_identifier verilogPullGateInstance, ## pull_gate_instance verilogPulldownStrength, ## pulldown_strength verilogPullupStrength, ## pullup_strength verilogPulseControlSpecparam, ## pulse_control_specparam verilogPulsestyleDeclaration, ## pulsestyle_declaration verilogQueueDimension, ## queue_dimension verilogRandcaseItem, ## randcase_item verilogRandcaseStatement, ## randcase_statement verilogRandomQualifier, ## random_qualifier verilogRandomizeCall, ## randomize_call verilogRangeExpression, ## range_expression verilogRealNumber, ## real_number verilogRefDeclaration, ## ref_declaration verilogReferenceEvent, ## reference_event verilogRejectLimitValue, ## reject_limit_value verilogRemainActiveFlag, ## remain_active_flag verilogRepeatRange, ## repeat_range verilogRestrictPropertyStatement, ## restrict_property_statement verilogScalarConstant, ## scalar_constant verilogScalarTimingCheckCondition, ## scalar_timing_check_condition verilogSelect1, ## select1 verilogSelectCondition, ## select_condition verilogSelectExpression, ## select_expression verilogSeqBlock, ## seq_block verilogSequenceAbbrev, ## sequence_abbrev verilogSequenceDeclaration, ## sequence_declaration verilogSequenceExpr, ## sequence_expr verilogSequenceFormalType1, ## sequence_formal_type1 verilogSequenceInstance, ## sequence_instance verilogSequenceListOfArguments, ## sequence_list_of_arguments verilogSequenceLvarPortDirection, ## sequence_lvar_port_direction verilogSequenceMethodCall, ## sequence_method_call verilogSequencePortItem, ## sequence_port_item verilogSequencePortList, ## sequence_port_list verilogSequentialBody, ## sequential_body verilogSequentialEntry, ## sequential_entry verilogShowcancelledDeclaration, ## showcancelled_declaration verilogSimpleImmediateAssertStatement, ## simple_immediate_assert_statement verilogSimpleImmediateAssumeStatement, ## simple_immediate_assume_statement verilogSimpleImmediateCoverStatement, ## simple_immediate_cover_statement verilogSimplePathDeclaration, ## simple_path_declaration verilogSimpleTextMacroUsage, ## simple_text_macro_usage verilogSliceSize, ## slice_size verilogSolveBeforeList, ## solve_before_list verilogSourceFile, ## source_file verilogSpecifyBlock, ## specify_block verilogSpecifyInputTerminalDescriptor, ## specify_input_terminal_descriptor verilogSpecifyOutputTerminalDescriptor, ## specify_output_terminal_descriptor verilogSpecparamAssignment, ## specparam_assignment verilogSpecparamDeclaration, ## specparam_declaration verilogSpecparamIdentifier, ## specparam_identifier verilogStartEdgeOffset, ## start_edge_offset verilogStateDependentPathDeclaration, ## state_dependent_path_declaration verilogStatement, ## statement verilogStatementItem, ## statement_item verilogStatementOrNull, ## statement_or_null verilogStreamConcatenation, ## stream_concatenation verilogStreamExpression, ## stream_expression verilogStreamOperator, ## stream_operator verilogStreamingConcatenation, ## streaming_concatenation verilogStrength0, ## strength0 verilogStrength1, ## strength1 verilogStringLiteral, ## string_literal verilogStructUnion, ## struct_union verilogStructUnionMember, ## struct_union_member verilogSubroutineCall, ## subroutine_call verilogSystemTfCall, ## system_tf_call verilogTaggedUnionExpression, ## tagged_union_expression verilogTaskBodyDeclaration, ## task_body_declaration verilogTaskDeclaration, ## task_declaration verilogTaskIdentifier, ## task_identifier verilogTaskPrototype, ## task_prototype verilogTerminalIdentifier, ## terminal_identifier verilogTextMacroDefinition, ## text_macro_definition verilogTextMacroIdentifier, ## text_macro_identifier verilogTextMacroName, ## text_macro_name verilogTextMacroUsage, ## text_macro_usage verilogTfCall, ## tf_call verilogTfIdentifier, ## tf_identifier verilogTfItemDeclaration, ## tf_item_declaration verilogTfPortDeclaration, ## tf_port_declaration verilogTfPortDirection, ## tf_port_direction verilogTfPortItem1, ## tf_port_item1 verilogTfPortList, ## tf_port_list verilogThreshold, ## threshold verilogTimeLiteral, ## time_literal verilogTimeUnit, ## time_unit verilogTimecheckCondition, ## timecheck_condition verilogTimescaleCompilerDirective, ## timescale_compiler_directive verilogTimestampCondition, ## timestamp_condition verilogTimeunitsDeclaration, ## timeunits_declaration verilogTimingCheckCondition, ## timing_check_condition verilogTimingCheckEvent, ## timing_check_event verilogTimingCheckEventControl, ## timing_check_event_control verilogTimingCheckLimit, ## timing_check_limit verilogTopmoduleIdentifier, ## topmodule_identifier verilogTransItem, ## trans_item verilogTransList, ## trans_list verilogTransRangeList, ## trans_range_list verilogTransSet, ## trans_set verilogTypeAssignment, ## type_assignment verilogTypeDeclaration, ## type_declaration verilogTypeReference, ## type_reference verilogUdpAnsiDeclaration, ## udp_ansi_declaration verilogUdpDeclaration, ## udp_declaration verilogUdpDeclarationPortList, ## udp_declaration_port_list verilogUdpInitialStatement, ## udp_initial_statement verilogUdpInputDeclaration, ## udp_input_declaration verilogUdpInstance, ## udp_instance verilogUdpInstantiation, ## udp_instantiation verilogUdpNonansiDeclaration, ## udp_nonansi_declaration verilogUdpOutputDeclaration, ## udp_output_declaration verilogUdpPortDeclaration, ## udp_port_declaration verilogUdpPortList, ## udp_port_list verilogUdpRegDeclaration, ## udp_reg_declaration verilogUnaryOperator, ## unary_operator verilogUnbasedUnsizedLiteral, ## unbased_unsized_literal verilogUnconnectedDrive, ## unconnected_drive verilogUniquePriority, ## unique_priority verilogUniquenessConstraint, ## uniqueness_constraint verilogUnpackedDimension, ## unpacked_dimension verilogUnsizedDimension, ## unsized_dimension verilogUseClause, ## use_clause verilogValueRange, ## value_range verilogVariableAssignment, ## variable_assignment verilogVariableDeclAssignment, ## variable_decl_assignment verilogVariableIdentifierList, ## variable_identifier_list verilogVariableLvalue, ## variable_lvalue verilogVariablePortHeader, ## variable_port_header verilogWaitStatement, ## wait_statement verilogZeroDirective, ## zero_directive verilogNewlineTok, ## ## verilogExclamationTok, ## ! verilogExclamationEqualTok, ## != verilogExclamationDoubleEqualTok, ## !== verilogExclamationEqualQuestionTok, ## !=? verilogQuoteTok, ## " verilogQuoteDPIQuoteTok, ## "DPI" verilogQuoteDPIMinusCQuoteTok, ## "DPI-C" verilogHashTok, ## # verilogDoubleHashTok, ## ## verilogDoubleHashLBrackAsteriskRBrackTok, ## ##[*] verilogDoubleHashLBrackPlusRBrackTok, ## ##[+] verilogHashMinusHashTok, ## #-# verilogHash0Tok, ## #0 verilogHashEqualHashTok, ## #=# verilogDollarTok, ## $ verilogDollarerorTok, ## $error verilogDollarfatalTok, ## $fatal verilogDollarfulskewTok, ## $fullskew verilogDollarholdTok, ## $hold verilogDollarinfoTok, ## $info verilogDollarnochangeTok, ## $nochange verilogDollarperiodTok, ## $period verilogDollarrecoveryTok, ## $recovery verilogDollarrecremTok, ## $recrem verilogDollarremovalTok, ## $removal verilogDollarrotTok, ## $root verilogDollarsetupTok, ## $setup verilogDollarsetupholdTok, ## $setuphold verilogDollarskewTok, ## $skew verilogDollartimeskewTok, ## $timeskew verilogDollarunitTok, ## $unit verilogDollarwarningTok, ## $warning verilogDollarwidthTok, ## $width verilogPercentTok, ## % verilogPercentEqualTok, ## %= verilogAmpersandTok, ## & verilogDoubleAmpersandTok, ## && verilogTripleAmpersandTok, ## &&& verilogAmpersandEqualTok, ## &= verilogApostropheTok, ## ' verilogApostrophe0Tok, ## '0 verilogApostrophe1Tok, ## '1 verilogApostropheB0Tok, ## 'B0 verilogApostropheB1Tok, ## 'B1 verilogApostropheb0Tok1, ## 'b0 verilogApostropheb1Tok1, ## 'b1 verilogApostropheLCurlyTok, ## '{ verilogLParTok, ## ( verilogLParAsteriskTok, ## (* verilogRParTok, ## ) verilogAsteriskTok, ## * verilogAsteriskRParTok, ## *) verilogDoubleAsteriskTok, ## ** verilogAsteriskDoubleColonAsteriskTok, ## *::* verilogAsteriskEqualTok, ## *= verilogAsteriskGreaterThanTok, ## *> verilogPlusTok, ## + verilogDoublePlusTok, ## ++ verilogPlusColonTok, ## +: verilogPlusEqualTok, ## += verilogCommaTok, ## , verilogMinusTok, ## - verilogDoubleMinusTok, ## -- verilogMinusColonTok, ## -: verilogMinusEqualTok, ## -= verilogMinusGreaterThanTok, ## -> verilogMinusDoubleGreaterThanTok, ## ->> verilogDotTok, ## . verilogDotAsteriskTok, ## .* verilogSlashTok, ## / verilogSlashEqualTok, ## /= verilog0Tok, ## 0 verilog01Tok, ## 01 verilog1Tok, ## 1 verilog1ApostropheB0Tok, ## 1'B0 verilog1ApostropheB1Tok, ## 1'B1 verilog1ApostropheBXTok, ## 1'BX verilog1ApostropheBxTok1, ## 1'Bx verilog1Apostropheb0Tok1, ## 1'b0 verilog1Apostropheb1Tok1, ## 1'b1 verilog1ApostrophebXTok2, ## 1'bX verilog1ApostrophebxTok3, ## 1'bx verilog10Tok, ## 10 verilog1stepTok, ## 1step verilog2Tok, ## 2 verilogColonTok, ## : verilogColonSlashTok, ## :/ verilogDoubleColonTok, ## :: verilogColonEqualTok, ## := verilogSemicolonTok, ## ; verilogLessThanTok, ## < verilogLessThanMinusGreaterThanTok, ## <-> verilogDoubleLessThanTok, ## << verilogTripleLessThanTok, ## <<< verilogTripleLessThanEqualTok, ## <<<= verilogDoubleLessThanEqualTok, ## <<= verilogLessThanEqualTok, ## <= verilogEqualTok, ## = verilogDoubleEqualTok, ## == verilogTripleEqualTok, ## === verilogDoubleEqualQuestionTok, ## ==? verilogEqualGreaterThanTok, ## => verilogGreaterThanTok, ## > verilogGreaterThanEqualTok, ## >= verilogDoubleGreaterThanTok, ## >> verilogDoubleGreaterThanEqualTok, ## >>= verilogTripleGreaterThanTok, ## >>> verilogTripleGreaterThanEqualTok, ## >>>= verilogQuestionTok, ## ? verilogAtTok, ## @ verilogAtAsteriskTok, ## @* verilogDoubleAtTok, ## @@ verilogPATHPULSEDollarEqualTok, ## PATHPULSE$= verilogLBrackTok, ## [ verilogLBrackAsteriskTok, ## [* verilogLBrackAsteriskRBrackTok, ## [*] verilogLBrackPlusRBrackTok, ## [+] verilogLBrackMinusGreaterThanTok, ## [-> verilogLBrackEqualTok, ## [= verilogLBrack–GreaterThanTok, ## [–> verilogBackslashTok, ## \ verilogRBrackTok, ## ] verilogAccentTok, ## ^ verilogAccentEqualTok, ## ^= verilogAccentTildeTok, ## ^~ verilogBacktickTok, ## ` verilogAcceptOnTok, ## accept_on verilogAliasTok, ## alias verilogAlwaysTok, ## always verilogAlwaysCombTok, ## always_comb verilogAlwaysFfTok, ## always_ff verilogAlwaysLatchTok, ## always_latch verilogAndTok, ## and verilogAssertTok, ## assert verilogAssignTok, ## assign verilogAssumeTok, ## assume verilogAutomaticTok, ## automatic verilogBeforeTok, ## before verilogBeginTok, ## begin verilogBinaryNumber, ## binary_number verilogBindTok, ## bind verilogBinsTok, ## bins verilogBinsofTok, ## binsof verilogBitTok, ## bit verilogBreakTok, ## break verilogBufTok, ## buf verilogBufif0Tok, ## bufif0 verilogBufif1Tok, ## bufif1 verilogByteTok, ## byte verilogCIdentifier, ## c_identifier verilogCaseTok, ## case verilogCasexTok, ## casex verilogCasezTok, ## casez verilogCellTok, ## cell verilogChandleTok, ## chandle verilogCheckerTok, ## checker verilogClassTok, ## class verilogClockingTok, ## clocking verilogCmosTok, ## cmos verilogComment, ## comment verilogConfigTok, ## config verilogConstTok, ## const verilogConstraintTok, ## constraint verilogContextTok, ## context verilogContinueTok, ## continue verilogCoverTok, ## cover verilogCovergroupTok, ## covergroup verilogCoverpointTok, ## coverpoint verilogCrossTok, ## cross verilogDeassignTok, ## deassign verilogDefaultTok, ## default verilogDefaultText, ## default_text verilogDefparamTok, ## defparam verilogDesignTok, ## design verilogDirectiveBeginKeywordsTok, ## directive_begin_keywords verilogDirectiveCelldefineTok, ## directive_celldefine verilogDirectiveDefaultNettypeTok, ## directive_default_nettype verilogDirectiveDefineTok, ## directive_define verilogDirectiveElseTok, ## directive_else verilogDirectiveElsifTok, ## directive_elsif verilogDirectiveEndKeywordsTok, ## directive_end_keywords verilogDirectiveEndcelldefineTok, ## directive_endcelldefine verilogDirectiveEndifTok, ## directive_endif verilogDirectiveIfdefTok, ## directive_ifdef verilogDirectiveIfndefTok, ## directive_ifndef verilogDirectiveIncludeTok, ## directive_include verilogDirectiveLineTok, ## directive_line verilogDirectiveNounconnectedDriveTok, ## directive_nounconnected_drive verilogDirectiveResetallTok, ## directive_resetall verilogDirectiveTimescaleTok, ## directive_timescale verilogDirectiveUnconnectedDriveTok, ## directive_unconnected_drive verilogDirectiveUndefTok, ## directive_undef verilogDirectiveUndefineallTok, ## directive_undefineall verilogDisableTok, ## disable verilogDistTok, ## dist verilogDoTok, ## do verilogEdgeTok, ## edge verilogEdgeSymbol, ## edge_symbol verilogElseTok, ## else verilogEndTok, ## end verilogEndcaseTok, ## endcase verilogEndcheckerTok, ## endchecker verilogEndclassTok, ## endclass verilogEndclockingTok, ## endclocking verilogEndconfigTok, ## endconfig verilogEndfunctionTok, ## endfunction verilogEndgenerateTok, ## endgenerate verilogEndgroupTok, ## endgroup verilogEndinterfaceTok, ## endinterface verilogEndmoduleTok, ## endmodule verilogEndpackageTok, ## endpackage verilogEndprimitiveTok, ## endprimitive verilogEndprogramTok, ## endprogram verilogEndpropertyTok, ## endproperty verilogEndsequenceTok, ## endsequence verilogEndspecifyTok, ## endspecify verilogEndtableTok, ## endtable verilogEndtaskTok, ## endtask verilogEnumTok, ## enum verilogEventTok, ## event verilogEventuallyTok, ## eventually verilogExpectTok, ## expect verilogExportTok, ## export verilogExtendsTok, ## extends verilogExternTok, ## extern verilogFinalTok, ## final verilogFirstMatchTok, ## first_match verilogFixedPointNumber, ## fixed_point_number verilogForTok, ## for verilogForceTok, ## force verilogForeachTok, ## foreach verilogForeverTok, ## forever verilogForkTok, ## fork verilogForkjoinTok, ## forkjoin verilogFsTok, ## fs verilogFunctionTok, ## function verilogGenerateTok, ## generate verilogGenvarTok, ## genvar verilogGlobalTok, ## global verilogHexNumber, ## hex_number verilogHighz0Tok, ## highz0 verilogHighz1Tok, ## highz1 verilogIfTok, ## if verilogIffTok, ## iff verilogIfnoneTok, ## ifnone verilogIgnoreBinsTok, ## ignore_bins verilogIllegalBinsTok, ## illegal_bins verilogImplementsTok, ## implements verilogImpliesTok, ## implies verilogImportTok, ## import verilogInitialTok, ## initial verilogInoutTok, ## inout verilogInputTok, ## input verilogInsideTok, ## inside verilogInstanceTok, ## instance verilogIntTok, ## int verilogIntegerTok, ## integer verilogInterconnectTok, ## interconnect verilogInterfaceTok, ## interface verilogIntersectTok, ## intersect verilogJoinTok, ## join verilogJoinAnyTok, ## join_any verilogJoinNoneTok, ## join_none verilogLargeTok, ## large verilogLetTok, ## let verilogLevelSymbol, ## level_symbol verilogLiblistTok, ## liblist verilogLocalTok, ## local verilogLocalparamTok, ## localparam verilogLogicTok, ## logic verilogLongintTok, ## longint verilogMacroText, ## macro_text verilogMacromoduleTok, ## macromodule verilogMatchesTok, ## matches verilogMediumTok, ## medium verilogModportTok, ## modport verilogModuleTok, ## module verilogMsTok, ## ms verilogNandTok, ## nand verilogNegedgeTok, ## negedge verilogNettypeTok, ## nettype verilogNewTok, ## new verilogNexttimeTok, ## nexttime verilogNmosTok, ## nmos verilogNoneTok, ## none verilogNorTok, ## nor verilogNoshowcancelledTok, ## noshowcancelled verilogNotTok, ## not verilogNotif0Tok, ## notif0 verilogNotif1Tok, ## notif1 verilogNsTok, ## ns verilogNullTok, ## null verilogOctalNumber, ## octal_number verilogOptionTok, ## option verilogOrTok, ## or verilogOutputTok, ## output verilogOutputSymbol, ## output_symbol verilogPackageTok, ## package verilogPackedTok, ## packed verilogParameterTok, ## parameter verilogPmosTok, ## pmos verilogPosedgeTok, ## posedge verilogPrimitiveTok, ## primitive verilogPriorityTok, ## priority verilogProgramTok, ## program verilogPropertyTok, ## property verilogProtectedTok, ## protected verilogPsTok, ## ps verilogPull0Tok, ## pull0 verilogPull1Tok, ## pull1 verilogPulldownTok, ## pulldown verilogPullupTok, ## pullup verilogPulsestyleOndetectTok, ## pulsestyle_ondetect verilogPulsestyleOneventTok, ## pulsestyle_onevent verilogPureTok, ## pure verilogRandTok, ## rand verilogRandcTok, ## randc verilogRandcaseTok, ## randcase verilogRandomizeTok, ## randomize verilogRcmosTok, ## rcmos verilogRealTok, ## real verilogRealtimeTok, ## realtime verilogRefTok, ## ref verilogRegTok, ## reg verilogRejectOnTok, ## reject_on verilogReleaseTok, ## release verilogRepeatTok, ## repeat verilogRestrictTok, ## restrict verilogReturnTok, ## return verilogRnmosTok, ## rnmos verilogRpmosTok, ## rpmos verilogRtranTok, ## rtran verilogRtranif0Tok, ## rtranif0 verilogRtranif1Tok, ## rtranif1 verilogSTok, ## s verilogSAlwaysTok, ## s_always verilogSEventuallyTok, ## s_eventually verilogSNexttimeTok, ## s_nexttime verilogSUntilTok, ## s_until verilogSUntilWithTok, ## s_until_with verilogSampleTok, ## sample verilogScalaredTok, ## scalared verilogSequenceTok, ## sequence verilogShortintTok, ## shortint verilogShortrealTok, ## shortreal verilogShowcancelledTok, ## showcancelled verilogSignedTok, ## signed verilogSimpleIdentifier, ## simple_identifier verilogSmallTok, ## small verilogSoftTok, ## soft verilogSolveTok, ## solve verilogSpecifyTok, ## specify verilogSpecparamTok, ## specparam verilogStaticTok, ## static verilogStdTok, ## std verilogStringTok, ## string verilogStrongTok, ## strong verilogStrong0Tok, ## strong0 verilogStrong1Tok, ## strong1 verilogStructTok, ## struct verilogSuperTok, ## super verilogSupply0Tok, ## supply0 verilogSupply1Tok, ## supply1 verilogSyncAcceptOnTok, ## sync_accept_on verilogSyncRejectOnTok, ## sync_reject_on verilogSystemTfIdentifier, ## system_tf_identifier verilogTableTok, ## table verilogTaggedTok, ## tagged verilogTaskTok, ## task verilogThisTok, ## this verilogThroughoutTok, ## throughout verilogTimeTok, ## time verilogTimeprecisionTok, ## timeprecision verilogTimeunitTok, ## timeunit verilogTranTok, ## tran verilogTranif0Tok, ## tranif0 verilogTranif1Tok, ## tranif1 verilogTriTok, ## tri verilogTri0Tok, ## tri0 verilogTri1Tok, ## tri1 verilogTriandTok, ## triand verilogTriorTok, ## trior verilogTriregTok, ## trireg verilogTypeTok, ## type verilogTypeOptionTok, ## type_option verilogTypedefTok, ## typedef verilogUnionTok, ## union verilogUniqueTok, ## unique verilogUnique0Tok, ## unique0 verilogUnsignedTok, ## unsigned verilogUnsignedNumber, ## unsigned_number verilogUntilTok, ## until verilogUntilWithTok, ## until_with verilogUntypedTok, ## untyped verilogUsTok, ## us verilogUseTok, ## use verilogUwireTok, ## uwire verilogVarTok, ## var verilogVectoredTok, ## vectored verilogVirtualTok, ## virtual verilogVoidTok, ## void verilogVoidApostropheTok, ## void' verilogWaitTok, ## wait verilogWaitOrderTok, ## wait_order verilogWandTok, ## wand verilogWeakTok, ## weak verilogWeak0Tok, ## weak0 verilogWeak1Tok, ## weak1 verilogWhileTok, ## while verilogWildcardTok, ## wildcard verilogWireTok, ## wire verilogWithTok, ## with verilogWithinTok, ## within verilogWorTok, ## wor verilogXnorTok, ## xnor verilogXorTok, ## xor verilogLCurlyTok, ## { verilogPipeTok, ## | verilogPipeMinusGreaterThanTok, ## |-> verilogPipeEqualTok, ## |= verilogPipeEqualGreaterThanTok, ## |=> verilogDoublePipeTok, ## || verilogRCurlyTok, ## } verilogTildeTok, ## ~ verilogTildeAmpersandTok, ## ~& verilogTildeAccentTok, ## ~^ verilogTildePipeTok, ## ~| verilog–Tok, ## – verilog–GreaterThanTok, ## –> verilog––Tok, ## –– verilogSyntaxError ## Tree-sitter parser syntax error
TsVerilogNode = distinct TSNode
VerilogParser = distinct PtsParser
VerilogNode = HtsNode[TsVerilogNode, VerilogNodeKind]

Procs

proc kind(node: TsVerilogNode): VerilogNodeKind {...}{.noSideEffect, raises: [Exception], tags: [RootEffect].}
proc tsNodeType(node: TsVerilogNode): string {...}{.raises: [], tags: [].}
proc newTsVerilogParser(): VerilogParser {...}{.raises: [], tags: [].}
proc parseString(parser: VerilogParser; str: string): TsVerilogNode {...}{. raises: [], tags: [].}
proc parseTsVerilogString(str: string): TsVerilogNode {...}{.raises: [], tags: [].}
proc treeReprTsVerilog(str: string; unnamed: bool = false): string {...}{. raises: [ValueError, Exception, NilArgumentError], tags: [RootEffect].}
proc toHtsNode(node: TsVerilogNode; str: ptr string): HtsNode[TsVerilogNode, VerilogNodeKind] {...}{.raises: [NilArgumentError, Exception], tags: [RootEffect].}
proc toHtsTree(node: TsVerilogNode; str: ptr string): VerilogNode {...}{. raises: [NilArgumentError, Exception], tags: [RootEffect].}
proc parseVerilogString(str: ptr string; unnamed: bool = false): VerilogNode {...}{. raises: [NilArgumentError, Exception], tags: [RootEffect].}
proc parseVerilogString(str: string; unnamed: bool = false): VerilogNode {...}{. raises: [NilArgumentError, Exception], tags: [RootEffect].}

Funcs

func isNil(node: TsVerilogNode): bool {...}{.raises: [], tags: [].}
func len(node: TsVerilogNode; unnamed: bool = false): int {...}{.raises: [], tags: [].}
func has(node: TsVerilogNode; idx: int; unnamed: bool = false): bool {...}{. raises: [], tags: [].}
func `$`(node: TsVerilogNode): string {...}{.raises: [Exception], tags: [RootEffect].}
func `[]`(node: TsVerilogNode; idx: int; kind: VerilogNodeKind | set[VerilogNodeKind]): TsVerilogNode

verilog_wrapper

Types

Procs

Funcs